library IEEE;
use IEEE.std_logic_1164.all;

entity zero_detector_n is
	generic (
		N : integer
	);
	port (
		d_i 	: in  std_logic_vector(N-1 downto 0);
		zero_o  : out std_logic
	);
end zero_detector_n;

architecture behav of zero_detector_n is

	signal result : std_logic;	

	function or_reduce(d : std_logic_vector)
	return std_logic is
		variable result : std_logic := '0';
	begin
		for i in 0 to (d'length - 1) loop
			result := d(i) or result;
		end loop;

		return result;
	end or_reduce;

begin

	zero_o <= not or_reduce(d_i);

end behav;
